When a power failure occurs, an information processing apparatus, such as a control module (CM), provided in a storage apparatus evacuates data in a cache memory that is under the control of a central processing unit (CPU), to a nonvolatile memory, using power from an interruption power supply unit, known as a system capacitor unit (SCU). After the information processing apparatus is started again, the data that has been evacuated (backed up) in the nonvolatile memory is restored to the cache memory and processing in the information processing apparatus is resumed. As used herein, any events where supply of power to the information processing apparatus is interrupted, such as a power failure, are collectively referred to as a “power failure”.
Although NAND flush memory cache memory devices have been traditionally used as the destinations to back up data, solid state drives (SSDs) compliant with the Serial Advanced Technology Attachment (SATA) standard (hereinafter, referred to SATA-SSDs) have become widely used.
Before power to a SATA-SSD is shut down, a power-off (P-OFF) sequence (SEQ) must be executed on that SATA-SSD, by executing commands, such as Standby, Standby Immediate, and Sleep. If the power is shut down without executing a power-off sequence, an exceptional power-off may arise, resulting in a failure of the SATA-SSD. Specifically, the Standby command is executed for placing a SATA-SSD into the standby mode, whereas the Standby Immediate command is executed for immediately placing a SATA-SSD into the standby mode. The Sleep command is executed for placing a SATA-SSD into the sleep mode. These commands and a power-off sequence are well-known in the ATA technologies, and their detailed description is thus omitted.
FIG. 14 is a diagram illustrating a configuration of a conventional information processing apparatus 101.
An information processing apparatus 101 includes a CPU 102, a memory controller 103, a cache memory 104, a power supply 105, an interruption power supply 106, a backup control unit 107, and a SATA-SSD 108.
The CPU 102 is a processing apparatus that performs various types of controls and computations, and embodies various functions by executing an operating system (OS) and programs.
The memory controller 103 controls transfers of data, between the CPU 102 and the cache memory 104, between the CPU 102 and the backup control unit 107, and between the cache memory 104 and the backup control unit 107.
The cache memory 104 is a memory with a higher access rate which temporarily stores data (user data) to be read from or written to the CPU 102. The cache memory 104 is generally provided within the CPU 102.
The SATA-SSD 108 is the destination memory to which data stored in the cache memory 104 is to be backed up upon a power failure. Hereinafter, the SATA-SSD 108 may also be simply referred to as the SSD 108.
The power supply 105 is a power supply that receives external AC power, and supplies DC power to the CPU 102, the memory controller 103, the cache memory 104, the interruption power supply 106, the backup control unit 107, and the SSD 108.
The interruption power supply 106 is an SCU including a capacitor 114. The interruption power supply 106 receives the DC power from the power supply 105, and accumulates the power in a capacitor 114. Upon a power failure, the interruption power supply 106 supplies the DC power accumulated in the capacitor 114, to the memory controller 103, the cache memory 104, the backup control unit 107, and the SSD 108.
The backup control unit 107 controls to back up data stored in the cache memory 104 to the SSD 108, upon a power failure, using DC power supplied from the interruption power supply 106.
The backup control unit 107 includes a Peripheral Component Interconnect Express (PCIe) interface (IF) control unit 121, a SATA IF unit 122, a non-data DMA unit 123, a write DMA unit 124, and a power failure sequence (SEQ) unit 125.
In the information processing apparatus 101, the memory controller 103 and the backup control unit 107 are connected via a PCIe link 111 which contains four lanes. Through the PCIe link 111, user data to be backed up from the cache memory 104 to the SSD 108 is sent from the cache memory 104 to the backup control unit 107 via the memory controller 103.
The backup control unit 107 is also connected to the SSD 108 via a SATA link 112. Through the SATA link 112, user data to be backed up from the cache memory 104 to the SSD 108 is sent from the backup control unit 107 to the SSD 108.
The PCIe IF control unit 121 is a processing unit that controls communications between the memory controller 103 and the backup control unit 107 through the PCIe link 111 in the information processing apparatus 101.
The SATA IF unit 122 is a processing unit that controls communications between the backup control unit 107 and the SSD 108 through the SATA link 112.
The non-data DMA unit 123 is a processing unit that transfers non-data, such as commands, between the memory controller 103 and the SSD 108. For example, the non-data DMA unit 123 instructs the SSD 108 to execute Standby Immediate such that a power-off sequence is executed after a write of backup data into the SSD 108 is completed.
The write DMA unit 124 is a processing unit that controls a write of user data between the memory controller 103 and the SSD 108, by means of direct memory access. For example, the write DMA unit 124 writes data to be backed up from the cache memory 104 to the SSD 108, from the cache memory 104 to the SSD 108 via the memory controller 103.
The power-off sequence unit 125 executes a power failure sequence, when a power failure to the information processing apparatus 101 arises.
The interruption power supply 106 supplies power throughout the lifetime (e.g., five years) of an information processing apparatus where data to be backed up, which might be considered as sufficient. However, since the time duration during which the capacitor 114 can supply power is gradually shortened due to aging, the capacity of the capacitor 114 upon a factory shipment of the information processing apparatus 101 is selected such that the capacitor 114 can supply power in a time duration which substantially equals twice the length of a power failure process, at the end of the lifetime of the information processing apparatus 101.
Hence, in several years after the information processing apparatus 101 was shipped from the factory, the interruption power supply 106 can supply sufficient power when a power failure arises. Accordingly, when a write error occurs in the SSD 108 while data is being backed up from the cache memory 104 to the SSD 108, data can be backed up in a reliable manner with the power from the interruption power supply 106.
Conventionally, the information processing apparatus 101 has a fixed maximum error retry count (e.g., 8) for writing backup data from the cache memory 104 to the SSD 108. Accordingly, power accumulated in the interruption power supply 106 may not be utilized for retrying to write backup data beyond the fixed maximum retry count. This means that power accumulated in the capacitor 114 may not be fully harnessed for more retries to write backup data when the interruption power supply 106 is not old.
On the contrary, as described above, shutting down of power supply to an SSD 108 without executing a power-off sequence may lead to an unexpected power-off, resulting in a failure of the SSD 108. Even in a fortunate case where the SSD 108 is not failed, the SSD 108 may experience an abnormally extended startup time or a first write to the SSD 108 may take an abnormally long time, after the information processing apparatus 101 is powered on.
For example, a power-on (P-ON) of an SSD 108 after such an unexpected power-off may be 100 times or more longer than a normal power-on time of the SSD 108. Additionally, time for a first write to the SSD 108 may be abnormally extended to several dozens of seconds, as oppose to several hundred milliseconds of normal write time.
As described above, since aging of the capacitor 114 in the interruption power supply 106 shortens the power feed duration of the capacitor 114, when a power failure arises, power from an old interruption power supply 106 may be used up during a write retry of backup data. In such a case, power supply to the SSD 108 is shut down before a power-off sequence is executed on the SSD 108. As described above, this may lead to an unexpected power-off of the SSD 108, resulting in a failure of the SSD 108.
Accordingly, in an information processing apparatus, improving the reliability of the information processing apparatus by appropriating adjusting a maximum retry count for a backup of data to a SATA-SSD is desirable.